1. Field of the Invention
The present invention generally relates to layout methods, computer aided design (CAD) apparatuses, program and storage media, and more particularly to a layout method for making a layout design that takes into consideration an electro migration (EM) when designing semiconductor integrated circuits and devices by CAD, a CAD apparatus that employs such a layout method, a computer-readable program for causing a computer to make such a layout design, and a computer-readable storage medium which stores such a program.
2. Description of the Related Art
According to the conventional layout design, the layout of transistors, passive devices or elements and the like is manually created by a layout designer (or creator) so as to satisfy an electro migration rule. In addition, the shapes of the elements are normally obtained by calculation using a technique different from that of an apparatus that makes the layout design, and the layout designer manually reflects the shapes of the elements to the layout of the elements that is obtained by satisfying the electro migration rule. For this reason, there is a possibility of introducing errors caused by human error at the time of the layout.
A check to confirm whether or not the electro migration rule is satisfied can only be made after the layout is completed. If the electro migration rule is not satisfied and an electro migration problem is found, there is a possibility that the elements must be rearranged by modifying the size, shape and the like of the elements. In such a case, however, a design modification from a bulk layer is inevitable because the size, shape and the like of the elements change, and consequently, the number of operation steps or processes of the layout increases.
FIG. 1 is a flow chart for explaining an example of a conventional layout method. In FIG. 1, a step S1 carries out a simulation of a circuit that is the design target (hereinafter simply referred to as a target circuit). A step S2 specifies maximum current values of the currents flowing between terminals of each of the elements forming the target circuit, and the shapes of the elements (hereinafter simply referred to as element shapes). A step S3 creates a layout of the elements so as to satisfy an electro migration rule, based on the specified maximum current values and element shapes. When the layout of the elements is completed, a step S4 arranges the elements by taking into consideration wirings, so as to create the layout of the target circuit. When the layout of the target circuit is completed, a step S5 carries out a layout verification. In addition, a step S6 carries out a layout judgement to confirm whether or not the layout of the target circuit satisfies a design rule check (DRC) rule and a layout versus schematic (LVS) rule. The process returns to the step S4 if the judgement result in the step S6 is NO. On the other hand, if the judgement result in the step S6 is YES, a step S7 carries out an electro migration check, and a step S8 carries out an electro migration judgement to confirm whether or not the layout of the target circuit satisfies the electro migration rule.
If the judgement result in the step S8 is NO, (a) an electro migration rule violation may be generated at a portion other than the elements or, (b) an electro migration rule violation may be generated within the layout of the elements. In the first case (a), the process returns to the step S4. However, in the latter case (b), there is a high possibility that the size, shape and the like of the elements will be changed by the modification of the layout of the elements, and the process returns to the step S3 since it is necessary to rearrange the elements. If the judgement result in the step S8 is YES, a step S9 completes the layout of the target circuit.
Japanese Laid-Open Patent Applications No.2000-349158 and No.2002-151592 propose layout methods and apparatuses that change the wiring width between cells and the shape of via holes depending on tolerable current values.
Therefore, according to the conventional layout method, the operation to satisfy the electro migration rule when making the layout of the elements was carried out manually. For this reason, it was impossible to completely create the layout satisfying the electro migration rule when making the layout of the elements. In order to make the electro migration check, the simulation must be carried out by extracting the verifying portion in a state where the layout of the elements is completed. Furthermore, if an electro migration rule violation exists within the layout of the elements, the modification of the layout may extend to the bulk layer, and there were problems in that the number of operation steps of processes of the layout is increased and the turn around time (TAT) is increased.